Formal Verification of Analog Circuits (FAC) '08

A satellite workshop at CAV 2008

July 14th, 2008, Princeton, US

Organizers: Oded Maler and Lars Hedrich

While formal verification has become part of the design process of digital circuits, its application to analog and mixed-signal design is still in its infancy. This is mainly due to the fact that the mathematical models for such circuits are very different from the discrete, finite-state transition systems that underly verification of digital systems. Such models are based on continuous dynamical systems governed by differential equations and their verification calls for different techniques, like those developed in the analysis of hybrid systems. This workshop intends to bring together practitioners in circuit design and in EDA tools together with researchers in verification of discrete and hybrid systems in order to understand the problems faced by designers of analog circuits and to see what support can be provided by existing and new verification techniques.

This is the second FAC workshop. Information about the first workshop, held in Edinburgh at 2005, can be found here.

Program committee:

  • Himyanshu Anand, Freescale, Austin
  • Bernd Becker, University of Freiburg
  • Partha P. Chakrabarti, IIT, Kharagpur
  • Avi Efrati, Intel, Haifa
  • Goran Frehse, UJF-Verimag, Grenoble
  • Mark Greenstreet, UBC, Vancouver
  • Lars Hedrich, University of Frankfurt
  • Kevin Jones, Rambus, Los Altos
  • Bruce Krogh, CMU, Pittsburgh
  • Oded Maler, CNRS-Verimag, Grenoble
  • Ken McMillan, Cadence, Berkeley Labs
  • Mark Moulin, IBM, Haifa
  • Chris Myers, University of Utah

  • List of accepted papers

    Technical program

    Invited talks:

  • Amir Pnuel, New York University and Weizmann Institute (Emeritus), USA
        Temporal Testers: The Building Blocks for Verification Automata    [abstract]
  • Victor Konrad, Rambus Inc., USA
        A Digital Verifier's Peek into the Analog World    [abstract]