Formal Verification of Analog Circuits (FAC) '08

List of accepted papers

Paper 1
Title: Abstract Modeling and Simulation Aided Verification of Analog/Mixed-Signal Circuits
Authors: S. Little and C. Myers

Paper 2
Title: Statistical Model Checking of Mixed-Analog Circuits
Authors: E. Clarke, A. Donze and A. Legay

Paper 3
Title: fSpice: A Boolean Satisfiability Based Approach to Formally Verifying Analog Circuits
Authors: S.K. Tiwary, A. Gupta, J.R. Phillips, C. Pinello and R. Zlatanovici

Paper 4
Title: A Bond Graph Approach for the Constraint based Verification of Analog Circuits
Authors: W. Denman, M.H. Zaki and S. Tahar

Paper 5
Title: Structural Methods for Equivalence Checking of Analog Circuits with Strong Nonlinearities
Authors: L. Hedrich and S. Steinhorst

Paper 6
Title: Analog Property Checkers: A DDR2 Case Study
Authors: K.D. Jones, V. Konrad and D. Nickovic