Frontiers in Analog CAD (FAC 2014)

Co-located with the CMOS-ET Symposium

July, 9-10, 2014

Grenoble, France

For FAC'17 see the VDE website here.


Even in pre-dominantly digital systems, modern chips integrate onto a single die a significant amount of analog content, including high speed IOs, memory interfaces, thermal sensors, and a multitude of PLLs. Despite the vast majority of the transistors being dedicated to the digital circuitry, the limited number of analog transistors often consume just as many design and verification resources. Using current methodologies, even well- understood analog circuits require nearly as much effort to modify and/or port to a new process as the initial design. Even when an analog circuit can be re-used, validating its performance within the new system – especially if the circuit is controlled through a digital loop – is often the long pole in the overall flow. The reasons for this situation are both technical and sociological; inherent differences in the behaviors of digital vs. analog systems make analog design and validation much more resistant to automation. Similarly, the cultural distance between the EDA software developers and analog designers is much larger than the distance between them and digital designers.

The goal of this workshop is to bring together technologists and researchers from analog design as well as CAD tool development to foster collaboration and exchange of ideas as well as to spur further research into the intersection of these domains. In this spirit, the workshop will be held in Grenoble, in co-location with the CMOS-ET symposium and in the neighborhood of analog EDA industry.

Invited Talks

  • Pierre Dautriche, ST Microelectronics

    "Will Silicon Proof Stay the Only Way to Verify Analog Circuits?"

  • Dejan Nickovic, Austrian Institute of Technology

    "Monitoring Mixed Signal Assertions - Theory, Tools and Applications"

  • Martin Vlach, Mentor Graphics

    "AMS Verification from Transistor to SoC"

  • Peter Rotter, Infineon, Munich

    "Analog Verification Concepts: Industrial Deployment Case Studies"



The workshop will take place at World-Trade-Center, Grenoble

Program Committee

  • Elad Alon, University of California, Berkeley
  • Emrah Acar, IBM, New York
  • Thao Dang, CNRS/VERIMAG, Grenoble
  • Goran Frehse, CNRS/VERIMAG, Grenoble
  • Serge Garcia-Sabiro, Mentor
  • Helmut Graeb, Technical Univ. of Munich
  • Mark Greenstreet, University of British Columbia
  • Christoph Grimm, University of Kaiserslautern
  • Chenjie Gu, Intel
  • Walter Hartong, Cadence
  • Lars Hedrich, University of Frankfurt
  • Mark Horowitz, Stanford University
  • Kevin Jones, City University London
  • Chandramouli Kashyap, Intel
  • Jeaha Kim, Seoul National University, South Korea
  • Peng Li, Texas A&M University
  • Xin Li, Carnegie Mellon University
  • Scott Little, Intel
  • Oded Maler, Verimag
  • Jean-Paul Morin, ST Microelectronics, France
  • Chris Myers, University of Utah
  • Sunderarajan S. Mohan, Synopsys
  • Frédéric Poullet, Dolphin Integration, Grenoble
  • Fahim Rahim, Atrenta, Grenoble
  • Rob Rutenbar, University of Illinois at Urbana-Champaign
  • Sebastian Steinhorst, TUM Create, Singapore

Program Chairs

  • Lars Hedrich, University Frankfurt, Germany
  • Jeaha Kim, Seoul National University, South Korea
  • Jean-Paul Morin, ST Microelectronics, France

Organization committee

  • Goran Frehse, Verimag, France
  • Thao Dang, Verimag, Grenoble
  • Oded Maler, Verimag

Steering Committee



Workshop History

This workshop is partly a successor of the FAC (formal verification of analog circuits) workshop held in 2005, 2008, 2009,2011,2013. Information about past workshops can be found at: