Formal Verification of Analog Circuits (FAC) '09

A satellite workshop of CAV 2009

June 26, 2009, Grenoble, France

Organizers: Goran Frehse and Lars Hedrich

Program of FAC'09

As formal verification techniques become more common in digital design, there is growing a demand for techniques to verify analog and mixed-signal circuits. The last two FAC workshops indicated an increasing interest in this topic from designers and EDA vendors as well as from the research community.

The analysis of continuous and mixed discrete-continuous systems is inherently difficult, and many different abstractions in combination with dedicated verification techniques are currently being investigated by researchers. This workshop intends to bring together practitioners in circuit design, EDA tool developers and researchers from discrete and hybrid systems verification. Its aim is to further the understanding of the problems faced by circuits designers and to improve modeling and verification techniques and their applicability to analog and mixed-signal circuits.

This is the third FAC workshop. Information about the first and second workshop, held 2005 and 2008 respectively, can be found here: FAC '05, FAC '08.

Program committee:

  • Himyanshu Anand, Freescale, Austin, USA
  • Bernd Becker, University of Freiburg, Germany
  • Partha P. Chakrabarti, Indian Institute of Technology, Kharagpur, India
  • Avi Efrati, Tel Aviv University, Israel
  • Martin Fraenzle, University of Oldenburg, Germany
  • Goran Frehse, UJF-Verimag, Grenoble, France
  • Mark Greenstreet, University of British Columbia, Canada
  • Lars Hedrich, University of Frankfurt, Germany
  • Kevin Jones, Green Plug, San Ramon, USA
  • Bruce Krogh, CMU, Pittsburgh, USA
  • Scott Little, Freescale, USA
  • Oded Maler, CNRS-Verimag, Grenoble, France
  • Ken McMillan, Cadence, Berkeley Labs, USA
  • Chris Myers, University of Utah, USA

  • Submission of abstracts:

    Authors are invited to send up to 10-15 pages abstracts   
    to fac("at")em.cs.uni-frankfurt.de not later than:April 15th extended to April 30th
    Notification of acceptance: May 15th
    USB-ready paper: June 15th